1. Field of the Invention
The present invention relates to a precharge circuit and semiconductor storage device equipped with this precharge circuit suitable for precharging bit lines comprising a memory cell array.
2. Description of the Related Art
With Dynamic Random Access Memory (DRAM) equipped with a memory cell array where memory cells comprised of memory capacitors and select transistors are connected in a matrix shape by a multiplicity of bit lines and word lines, information is first read from the memory cells and the same prescribed potentials are applied to bit line pairs.
When the word line relating to the memory cell to be read from of the bit line pairs to which a potential has been applied is ascertained, a select transistor relating to this memory cell conducts. A load of a memory capacitor of the memory cell taken as the target is then discharged to one of the bit lines. A change in potential of one of the bit lines due to this discharged load is then sensed at a sense amplifier by making a comparison with the potential of the remaining bit line so that information of this memory cell is read.
In order to carry out the above precharge operation, a precharge circuit in which prescribed potentials are applied to bit line pairs comprises a precharge power supply for setting equal potentials at bit lines extending in parallel spaced on a semiconductor substrate, pairs of switching elements for putting the precharge power supply to bit line pairs on and off and short circuit switching elements for shorting bit lines in order to supply the same potential to selected bit line pairs.
The switching elements for this precharge circuit are comprised of MOS transistors having sources and drains constituted by pairs of impurity regions formed on a semiconductor substrate with gates formed between theses sources and gates.
With related MOS transistors constituting short circuit switching elements of the MOS transistors of precharge circuits, a pair of impurity regions for a source and drain corresponding to this bit line are formed at a certain bit line of a pair of bit lines and a gate having a gate length that is in the direction of extension of the bit lines and that lies between the bit lines is formed between the pair of impurity regions.
Increasing the gate width of the MOS transistors comprising the short circuit switching elements has been considered in order to increase the speed of precharging for setting prescribed equal potentials to the hit lines for short periods of time.
The gate length of gates of the short circuit switching elements are formed so as to extend along the direction of extension of the bit lines between bit line pairs. However, increasing the gate width in a direction at right angles to the gate length invites increases in the distances between certain bit lines of bit line pairs.